7세그먼트 디코더 vhdl 중인데요... 토할꺼 같아요 제발 도와주세요 <div>도대체 왜 왜왜왜왜 에러가 뜨죠 하 몇번을 지우고해도 무한 에러</div> <div>하다하다 지쳐서 도움 요청합니다..</div> <div><div><br></div> <div>library ieee;</div> <div>use ieee.std_logic_1164.all;</div> <div>use ieee.std_logic_unsigned.all;</div> <div>use ieee.std_logic_arith.all;</div> <div><br></div> <div>entity lab is</div> <div> port( clk : in std_logic;</div> <div> key : in std_logic_vector(15 downto 0);</div> <div> seg : out std_logic_vector(6 downto 0));</div> <div> end lab;</div> <div><br></div> <div>architecture design of lab is</div> <div>begin</div> <div> -- process for key input</div> <div> process(clk, key)</div> <div> begin</div> <div> if rising_edge(clk) then</div> <div> case key(15 downto 0) is</div> <div> when "0000000000000001" => seg <= "1111110";</div> <div> when "0000000000000010" => seg <= "0110000";</div> <div> when "0000000000000100" => seg <= "1101101";</div> <div> when "0000000000001000" => seg <= "1111001";</div> <div> when "0000000000010000" => seg <= "0110011";</div> <div> when "0000000000100000" => seg <= "1011011";</div> <div> when "0000000001000000" => seg <= "1011111";</div> <div> when "0000000010000000" => seg <= "1110000";</div> <div> when "0000000100000000" => seg <= "1111111";</div> <div> when "0000001000000000" => seg <= "1110011";</div> <div> when "0000010000000000" => seg <= "1111101";</div> <div> when "0000100000000000" => seg <= "0011111";</div> <div> when "0001000000000000" => seg <= "0001101";</div> <div> when "0010000000000000" => seg <= "0111101";</div> <div> when "0100000000000000" => seg <= "1101111";</div> <div> when "1000000000000000" => seg <= "1000111";</div> <div> when others => null;</div> <div> end case;</div> <div> end if;</div> <div> end process;</div> <div> end design;</div> <div> </div></div>
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